1. Field of the Invention
The present invention relates generally to methods for fabricating microelectronic fabrications. More particularly, the present invention relates to self-aligned methods for fabricating microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased and microelectronic device and patterned microelectronic conductor layer dimensions have decreased, it has become increasingly common within the art of microelectronic fabrication to employ self-aligned methods to form self-aligned microelectronic structures within microelectronic fabrications. Self-aligned methods for forming self-aligned microelectronic structures within microelectronic fabrications are common and desirable in the art of microelectronic fabrication insofar as self-aligned methods for forming self-aligned microelectronic structures within microelectronic fabrications by their nature avoid when forming the self-aligned microelectronic structures within the microelectronic fabrications the use of photolithographic methods. In turn, it is clearly also desirable to avoid when fabricating microelectronic structures within microelectronic fabrication the use of photolithographic methods insofar as photolithographic methods provide photolithographic misregistration tolerances when forming microelectronic structures within the microelectronic fabrications.
While self-aligned methods are thus clearly desirable within the art of microelectronic fabrication for forming self-aligned microelectronic structures within microelectronic fabrications, self-aligned methods are nonetheless not entirely without problems in the art of microelectronic fabrication for forming self-aligned microelectronic structures within microelectronic fabrications.
In that regard, self-aligned methods, while desirable insofar as they avoid photolithographic misregistration tolerances when fabricating self-aligned microelectronic structures within microelectronic fabrications, nonetheless typically suffer from problems such as but not limited to over-etching problems, in particular under circumstances where, for example, a self-aligned method is employed for forming a high aspect ratio self-aligned via interposed between a pair of high aspect ratio microelectronic structures within a microelectronic fabrication. In particular, such problematic over-etching may be needed to completely clear the surface of a conductor layer which is accessed by the high aspect ratio self-aligned via. Similarly, such over-etching may provide for reliability problems with respect to electrical performance of a conductor stud layer which is subsequently formed into the high aspect ratio self-aligned via within the microelectronic fabrication.
It is thus desirable in the art of microelectronic fabrication to provide self-aligned methods through which may be formed with enhanced reliability self-aligned microelectronic structures within microelectronic fabrications.
It is towards the foregoing object that the present invention is directed.
Various self-aligned methods have been disclosed in the art of microelectronic fabrication for forming various self-aligned microelectronic structures with desirable properties within microelectronic fabrications.
For example, Murali et al., in U.S. Pat. No. 4,966,868, discloses a self-aligned method for forming, with enhanced junction integrity, a self-aligned conductor contact stud filling a contact via which accesses a silicon semiconductor substrate within a semiconductor integrated circuit microelectronic fabrication. To realize the foregoing object, the self-aligned method employs forming within the contact via the self-aligned conductor contact stud formed at least in part of a polysilicon material formed employing a selective deposition method.
In addition, Pan, in U.S. Pat. No. 5,854,127, discloses a self-aligned method for forming within a microelectronic fabrication a landing pad layer in contact with a polysilicon conductor contact stud, wherein the landing pad layer is formed of areal dimensions greater than the polysilicon conductor contact stud. To realize the foregoing object, the self-aligned method employs in a first instance the polysilicon conductor contact stud formed interposed between a pair of microelectronic structures within the microelectronic fabrication, wherein upon thermal annealing of a metal silicide forming metal layer formed upon the polysilicon conductor contact stud and spanning to the pair of microelectronic structures within the microelectronic fabrication there is formed a metal. silicide landing pad layer of areal dimensions greater than the polysilicon conductor contact stud.
Further, Nguyen et al., in U.S. Pat. No. 5,956,615, discloses an in-part self-aligned method for forming within a microelectronic fabrication a landing pad layer in contact with a conductor stud in such a manner as to reduce an aspect ratio of an interconnection via subsequently formed through a dielectric layer which passivates the landing pad layer in contact with the conductor stud. To realize the foregoing object, the in-part self-aligned method preferably employs when forming both the conductor stud and the landing pad layer a doped polysilicon material formed as a single layer.
Finally, Jeng et al., in U.S. Pat. No. 6,037,211, discloses a self-aligned method for forming within a semiconductor integrated circuit microelectronic fabrication a conductor contact stud in a fashion such as to provide for enhanced contact area of the conductor contact stud when forming an additional conductor layer in contact with the conductor contact stud. To realize the foregoing object, the method employs when forming the conductor contact stud while employing the self-aligned method a mask layer having formed at its periphery an annular conductor layer which supplements the conductor contact stud at its upper periphery such as to provide the conductor contact stud with enhanced contact area.
Desirable in the art of microelectronic fabrication are additional self-aligned methods which may be employed for forming, with enhanced reliability, self-aligned microelectronic structures within microelectronic fabrications.
It is towards the foregoing object that the present invention is directed.